Publication number | Date of Publication | Review date | Result date | Technical Comittee | Project in progress |
|---|
EN 61523-1:2002 (pr=14109) Delay and power calculation standards - Part 1: Integrated circuit delay and power calculation systems | 2002-01-11 | | 2010-01-11 | CLC/SR 93 | |
EN 61690-1:2000 (pr=11772) Electronic Design Interchange Format (EDIF) - Part 1: Version 3 0 0 | 2000-05-23 | | 2008-05-23 | CLC/SR 93 | |
EN 61690-2:2000 (pr=11780) Electronic Design Interchange Format (EDIF) - Part 2: Version 4 0 0 | 2000-05-23 | | 2008-05-23 | CLC/SR 93 | |
EN 61691-2:2001 (pr=14348) Behavioural languages - Part 2: VHDL multilogic system for model interoperability | 2001-12-14 | | 2009-12-14 | CLC/SR 93 | |
EN 61691-3-3:2001 (pr=14351) Behavioural languages - Part 3-3: Synthesis in VHDL | 2001-12-14 | | 2009-12-14 | CLC/SR 93 | |
EN 61926-1:2000 (pr=13238) Design automation - Part 1: Standard test language for all systems - Common abbreviated test language for all systems (C/ATLAS) | 2000-01-24 | | 2008-01-24 | CLC/SR 93 | |
EN 62014-1:2002 (pr=12876) Electronic design automation libraries - Part 1: Input/Output buffer information specifications (IBIS version 3.2) | 2002-01-11 | | 2010-01-11 | CLC/SR 93 | |